1. Field of the Invention
The present invention relates to thin film transistors (hereinafter referred to as TFTs) and to manufacturing methods therefor, and more particularly, to a TFT structure in which copper is used as a low resistance material specifically for source and drain wiring.
2. Description of the Related Art
In conventional common TFT liquid crystal display devices, a TFT array substrate having a reverse-stagger type TFT, gate wiring, source wiring, and the like is provided, as shown in FIG. 6 as a structural example. In the TFT array substrate, as shown in FIG. 6, gate wiring 50 and source wiring 51 are disposed in the form of a matrix on a transparent substrate composed of glass or the like. An area surrounded by the gate wiring 50 and the source wiring 51 is a pixel 52, and a TFT 53 is formed in each pixel 52. Recently, copper, which is a low resistance material, has attracted attention as a wiring material for use in this kind of liquid crystal display device, semiconductor device, and the like. Accordingly, one example will be described below in which copper is applied to a TFT array substrate. FIG. 4 is a cross-sectional view of the TFT array substrate, and FIGS. 5A to 5E are cross-sectional views of the TFT showing a manufacturing process therefor.
In the TFT 53 as shown in FIG. 4, a gate electrode 55 extending from the gate wiring 50 is formed on a transparent substrate 54, and a gate insulation film 56 is formed so as to cover the gate electrode 55. A semiconductor active layer 57 composed of amorphous silicon (a-Si) is formed on the gate insulation film 56 above the gate electrode 55. A source electrode 59 extending from the source wiring 51 and a drain electrode 60 are formed above ohmic contact layers 58 formed on the semiconductor active layer 57 above the gate insulation film 56, in which the ohmic contact layers 58 are composed of amorphous silicon (a-Si:n+) containing an n-type impurity such as phosphorus. The source wiring 51, source electrode 59, and the drain electrode 60 are formed of copper.
When the source electrode 59 and the drain electrode 60 are formed of copper, and when silicon forming the semiconductor active layer 57 and copper are placed directly in contact with each other, a problem arises with regard to copper film separation due to poor cohesion between silicon and copper, or degradation of TFT characteristics due to copper diffusion into silicon. Consequently, metal layers composed of, for example, titanium or molybdenum, are formed under the copper as barrier metal layers 61 so that the source wiring 51, the source electrode 59, and the drain electrode 60 have a two-layer structure composed of a barrier metal and copper.
Then, a passivation film 62 is formed so as to cover the TFT 53 composed of the source electrode 59, the drain electrode 60, the gate electrode 55, and the like. A contact hole 63 is formed in the passivation film 62 above the drain electrode 60. A pixel electrode 64 is further formed, which is composed of a transparent conductive film, such as an indium-tin-oxide compound (hereinafter referred to as ITO), and is electrically connected to the drain electrode 60 via the contact hole 63.
A left side of the discontinuity in FIG. 4 shows a cross-sectional structure of a gate terminal pad portion 65 which is an end portion of the gate wiring located outside the display area. As shown in this figure, a contact hole 67 penetrating the gate insulation film 56 and the passivation film 62 is formed above a lower pad layer 66 composed of a gate wiring material on the transparent substrate 54, and an upper pad layer 68 is formed of the same transparent conductive film as that used for the pixel electrode 64 so as to be electrically connected with the lower pad layer 66 via the contact hole 67.
When the thin film transistor array substrate is manufactured, as shown in FIG. 5A, a conductive film is formed on the transparent substrate 54, and is then patterned, so that the gate electrode 55 and the gate wiring 50 are formed. In addition, the lower pad layer 66 is formed in the gate terminal pad portion 65.
Next, as shown in FIG. 5B, after forming the gate insulation film 56 so as to cover the gate electrode 55 and the gate wiring 50, an a-Si film (to later become semiconductor active layer 57), and an a-Si:n+ film 69 are sequentially formed, and the a-Si film and the a-Si:n+ film 69 thus formed are simultaneously patterned by using a photo mask, whereby an island 70 is formed above the gate electrode with the gate insulation film 56 provided therebetween.
As shown in FIG. 5C, after sequentially forming the barrier metal film 61 composed of, for example, titanium or molybdenum, and a copper film 71 over the entire surface of the substrate, the copper film 71 and the barrier metal film 61 are patterned so as to form the drain electrode 60, the source electrode 59, and the source wiring 51, and the a-Si:n+ film above a channel region composed of the a-Si film is removed so as to form the ohmic contact layers 58 composed of the a-Si:n+ film.
Next, as shown in FIG. 5D, the passivation film 62 is formed over the entire surface of the substrate, and is then patterned so as to form openings therein above the drain electrode 60 and the lower pad layer 66, whereby the contact holes 63 and 67 are formed for electrical connections between the drain electrode 60 and the pixel electrode 64 and between the lower pad layer 66 and the upper pad layer 68, respectively.
Finally, as shown in FIG. 5E, the ITO film is formed over the entire surface of the substrate, and is then patterned so as to form the pixel electrode 64 and the upper pad layer 68. By executing the steps described above, the conventional TFT array substrate shown in FIG. 4 is completed.
However, in the conventional TFT array substrate, there are problems as described below.
That is, since the source electrode and the drain electrode are laminates each composed of the barrier metal layer (titanium, molybdenum, or the like) and copper, a cell reaction occurs between the titanium, molybdenum, or the like and the copper when the laminate is etched, and as a result, undercuts in the barrier metal layer are formed at the side surfaces of the pattern. When the undercuts are formed at the above-mentioned location, there are problems with regard to an increase in off-current of the TFT and worsening of residual images. In addition, the wiring widths are difficult to control due to the occurrence of the undercuts in the barrier metal layer, and as a result, there is a problem in that desired characteristics of the TFT cannot be obtained. Furthermore, even though the copper, which is a low resistance material, is used, the barrier metal layer having a higher resistance than that of copper is used as an under layer, and hence, the advantages of copper which has a lower resistance are not sufficiently exploited.
In order to solve the problems described above, an object of the present invention is to provide a TFT structure and a manufacturing method therefor, in which characteristic defects in the TFT can be prevented, which were caused by undercuts in a barrier metal layer formed in a step for processing a source electrode and a drain electrode composed of copper, and a low resistance wiring can thereby be adequately realized.
To these ends, the TFT of the present invention comprises a gate electrode formed on a substrate, a gate insulation film formed so as to cover the gate electrode, a semiconductor active layer formed on the gate insulation film so as to oppose the gate electrode, ohmic contact layers formed of a doped semiconductor layer and separately formed on two edge portions of the semiconductor active layer, and a source electrode and a drain electrode connected to the semiconductor active layer via the respective ohmic contact layers, wherein the source electrode and the drain electrode are composed of copper, and barrier metal layers are formed on the bottom surfaces of the source electrode and the drain electrode above areas at which the upper surfaces of the respective ohmic contact layers are located.
In conventional TFT structures, when copper is used as a material for a source and a drain electrode, a barrier metal layer is formed on the entire bottom surface of the copper layer, and the overall electrode (wiring) is generally a two-layer structure. In contrast, in the TFT structure of the present invention, the barrier metal layers are formed on the bottom surfaces of the source electrode and the drain electrode above areas at which the upper surfaces of the ohmic contact layers are located, and the barrier metal layers are not formed on other areas at which the upper surfaces of the gate insulation film are located.
In order to practically form the structure described above, since the barrier metal layer and the copper layer cannot be formed by simultaneous patterning, the copper film is formed after forming the barrier metal layer by patterning. Consequently, unlike in conventional methods in which a laminate composed of a barrier metal layer and a copper layer is formed by simultaneous etching, undercuts in the barrier metal layer are not formed, which is caused by a cell reaction during etching. As a result, characteristic defects of the TFT caused by the undercuts formed in the barrier metal layer can be prevented. In addition, since the barrier metal layers are only present above areas at which the ohmic contact layers are formed, and the source wiring portion is only formed of, for example, copper, resistance of the wiring can be lowered compared to that of the conventional wiring.
As a material used for the barrier metal layer, a metal selected from the group consisting of titanium, molybdenum, tantalum, chromium, and tungsten, or an alloy thereof may be used.
A method for manufacturing a thin film transistor comprises steps of forming an electrically conductive film on a substrate, patterning the electrically conductive film to form a gate electrode, forming a gate insulation film so as to cover the gate electrode, a semiconductor film, a doped semiconductor film doped with an impurity, and a barrier metal film in that order, patterning the barrier metal film, the doped semiconductor film, and the semiconductor film so as to form a laminated island having a semiconductor active layer formed of the semiconductor film, the doped semiconductor film, and the barrier metal film, forming a copper film so as to cover the laminated island and the gate insulation film, patterning the copper film so as to form a source electrode and a drain electrode extending from the laminated island onto the gate insulation film, and removing the barrier metal film and the doped semiconductor film by etching using the source electrode and the drain electrode as a mask so that ohmic contact layers formed of the doped semiconductor film and patterned layers formed of the barrier metal film are present above the two edge portions of the semiconductor active layer.
According to the method for manufacturing the TFT described above, the TFT structure of the present invention can be formed. In the TFT structure of the present invention, as described above, patterning of the barrier metal film and the patterning of the copper film are separately performed. However, after sequentially forming the four films, i.e., the gate insulation film, the semiconductor film, the doped semiconductor film, and the barrier metal film, a laminated island having the semiconductor active layer, the doped semiconductor film, and the barrier metal film is formed by patterning the barrier metal film, the doped semiconductor film, and the semiconductor film. That is, in the manufacturing method of the present invention, since the barrier metal film is simultaneously patterned with the semiconductor active layer and the doped semiconductor film in a step for forming the laminated island, only barrier metal film is not separately patterned. Accordingly, compared to the conventional manufacturing process, the number of photomasks to be used is not increased.
In the manufacturing method described above, the gate insulation film, the semiconductor film, the doped semiconductor film, and the barrier metal film are preferably sequentially formed without being exposed in the air. When the four-layer formation mentioned above is performed, oxide layers are not formed between four layers, and as a result, the characteristics of the TFT are not adversely affected. In addition, steps for removing oxide layers can be omitted, and hence, the number of manufacturing steps can be reduced.
Film formation described above can be realized by using, for example, chemical vapor deposition (CVD). For example, a gate insulation film composed of a silicon oxide film or a silicon nitride film, a semiconductor film and a doped semiconductor film composed of amorphous silicon or polycrystalline silicon, and a barrier metal film composed of various metals can be formed by changing ingredient gases using one CVD apparatus. When the barrier metal film, in particular, is formed using metal organic chemical vapor deposition (hereinafter referred to as MOCVD), all four layers can be formed by CVD.
In another thin film transistor in accordance with the basic structure of the thin film transistor according to the present invention, the barrier metal layer may comprise titanium, and titanium oxide layers may be formed between the source electrode and the barrier metal layer and between the drain electrode and the barrier metal layer.
Another method for manufacturing a thin film transistor according to the present invention comprises steps of forming an electrically conductive film on a substrate, patterning the electrically conductive film so as to form a gate electrode, forming a gate insulation film so as to cover the gate electrode, a semiconductor film, a doped semiconductor film doped with an impurity, and a barrier metal film comprising titanium in that order, patterning the barrier metal film, the doped semiconductor film, and the semiconductor film so as to form a laminated island having a semiconductor active layer formed of the semiconductor film, the doped semiconductor film, and the barrier metal film, forming a copper film so as to cover the laminated island and the gate insulation film, patterning the copper film and the barrier metal film by using the same etchant so as to form a source electrode and a drain electrode extending from the laminated island onto the gate insulation film, and removing the doped semiconductor film by etching using the source electrode and the drain electrode as a mask so that ohmic contact layers formed of the doped semiconductor film and patterned layers formed of the barrier metal film are present above the two edge portions of the semiconductor active layer.
In the basic structure of the thin film transistor according to the present invention, when titanium is used, particularly for the barrier metal layer, portions of the source electrode and the drain electrode located above the semiconductor active layer are a two-layer structure composed of titanium and copper. The inventors of the present invention found etchants capable of simultaneously etching a laminate composed of titanium and copper. They are, specifically, an aqueous solution containing monohydrogen potassium peroxomonosulfate and hydrogen fluoride; an aqueous solution containing a peroxosulfate salt, hydrogen fluoride, and hydrogen chloride or a chloride compound; and an aqueous solution containing a peroxosulfate salt and a fluoride. Accordingly, even though patterning separately performed for the barrier metal film and the copper film is described heretofore, instead of the manufacturing method described above, patterning of the barrier metal film and patterning of the source electrode and the drain electrode can be simultaneously performed by applying the etchants to the present invention. The patterning of the barrier metal film in this case is specifically to remove the barrier metal film formed above a channel region of the TFT in the laminated island.
However, when the laminated film composed of titanium and copper is etched using the etchant described above, etching residue may remain on the ohmic contact layer and the gate insulation film in some cases, resulting in variations in the TFT characteristics or degradation of reliability. In this case, when a laminated structure is formed so as to have a titanium oxide layer between the titanium and the copper, uniformity obtained in the simultaneous etching is improved, and hence, the problems described above are unlikely to occur.
In the basic structure of the thin film transistor according to the present invention, the semiconductor active layer is preferably in direct contact with the source electrode and the drain electrode at two edge surfaces of the semiconductor active layer, and the two edge surfaces of the semiconductor active layer are preferably formed at positions outside areas defined by projecting the gate electrode to the gate insulation film.
In the thin film transistor of the present invention, since the barrier metal layers are only present above the areas at which the upper surfaces of the ohmic contact layers are located, the semiconductor active layer are in direct contact with the source electrode and the drain electrode at the two edge surfaces of the semiconductor active layer. In this case, when contacting points therebetween are close to the gate electrode, the electric fields from the gate electrode adversely affect the contacting points, resulting in a problem with regard to an increase in off-current of the TFT. Consequently, the contacting points are formed so as to be distant from the positions defined by projecting the gate electrode to the gate insulation film, i.e., the contacting points are preferably formed distant from the ends of the gate electrode so as not to be adversely affected by the electric fields from the gate electrode. Accordingly, the problems with regard to an increase in off-current can be avoided.